DESIGN VERIFICATION (DV) ENGINEER
(On-site, Full Time)

Exciting opportunity alert! We’re hiring a Design Verification Engineer for a full-time on-site position. If you’re skilled in chip verification and ready to make a difference, we want to hear from you!

QUALIFICATIONS

• Proven ability to actively contribute to IP/SoC-level design and/or verification projects, digital logic design, and implementation from a microarchitectural chip/sub-system/sub-block level.

• Proven track record in working with teams involved in a wide variety of system disciplines (SoC Designers, micro-architects, firmware, etc.) to formulate, implement, and execute verification plans and strategies.

>3+ years working experience in UVM, embedded C-based firmware co-simulation, and formal property verification; in any of the following Languages: C, C++/System C, PERL, Python, Java, Verilog/VHDL, SystemVerilog.

• Familiarity with or Experience in two or more of the following:
       –   ASIC/SOC Design Flows including Synthesis, DFT, STA, UPF, and ECO flows;
       –   Low Power design techniques;
       –   NVMe, SATA, PCIe, DDR, or ARM standards;
       –   Big Box Emulation platforms;
       –   Formal Verification methods.

• Robust debugging and problem-solving skills supported by relevant experience.
• Excellent written and verbal communication skills.
• Having an active nonimmigrant US visa or Canada visa/eTA is a plus.

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