Looking for a leadership role with flexibility? Look no further! Join us as a Design Verification (DV) Manager in this flexible/hybrid, full-time position. Lead with agility and shape the future of technology.


Leadership skills in spearheading a team of design verification engineers; able to effectively and efficiently manage and organize program and project resources to produce outcomes for the overall success of the business unit and deliver impactful results to stakeholders through the team; able to work closely with Top Management to formulate and deliver strategies for capability building and sustaining, and the institutional growth of the business unit by fostering good customer relations management.

• Proven ability to lead IP/SoC-level design and/or verification projects with a proven track record of collaborating closely with teams in a wide variety of system disciplines (SoC Designers, micro-architects, firmware, etc.) to formulate, implement and execute verification plans and strategies.

>15+ years of working experience in UVM, embedded C-based firmware co-simulation, and formal property verification; in any of the following Languages: C, C++/System C, PERL, Python, Java, Verilog/VHDL, SystemVerilog.

• Familiarity with or Experience in two or more of the following:
     – ASIC/SOC Design Flows including Synthesis, DFT, STA, UPF, and ECO flows;
     – Low Power design techniques;
     – NVMe, SATA, PCIe, DDR, or ARM standards;
     – Big Box Emulation platforms;
     – Formal Verification methods.

• Robust debugging and problem-solving skills supported by relevant experience.
• Excellent written and verbal communication skills.
• Having an active nonimmigrant US visa or Canada visa/eTA is a plus.