SENIOR DESIGN VERIFICATION (DV) ENGINEER (Hybrid, Full Time)
Are you a seasoned DV Engineer ready to make your mark in a hybrid work environment? Look no further! Join our team as a Senior DV Engineer and play a pivotal role in shaping the future of technology.
QUALIFICATIONS
• Proven ability to architect and lead IP/SoC-level design and/or verification projects, digital logic design, and implementation from an architectural or microarchitectural level.
• Proven track record in working with teams involved in a wide variety of system disciplines (SoC Designers, micro-architects, firmware, etc.) to formulate, implement, and execute verification plans and strategies.
• >10+ years of working experience in UVM, embedded C-based firmware co-simulation, and formal property verification; in any of the following Languages: C, C++/System C, PERL, Python, Java, Verilog/VHDL, SystemVerilog.
• Familiarity with or Experience in two or more of the following:
– ASIC/SOC Design Flows including Synthesis, DFT, STA, UPF, and ECO flows;
– Low Power design techniques;
– NVMe, SATA, PCIe, DDR, or ARM standards;
– Big Box Emulation platforms;
– Formal Verification methods.
• Robust debugging and problem-solving skills supported by relevant experience.
• Excellent written and verbal communication skills.
• Having an active nonimmigrant US visa or Canada visa/eTA is a plus.