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EXPERIENCED IC LAYOUT ENGINEER

SilVer is seeking passionate, experienced IC Layout Engineers who are committed to making a difference in the world through their contributions. The candidates will collaborate with our clients and SilVer Design Team in designing and developing complex and detailed layout designs for various integrated circuits. Candidates should have at least 5+ years of proven in-depth experience on full-custom and semi-custom layouts of various IPs, memory cells, analog blocks, and fullchip integration. In addition, the candidates are expected to work with stakeholders to plan schedules, provide test cases, and resolve design issues.

ACCOUNTABILITIES

Implement full-custom layout design of IPs up to fullchip integration.Implement different types of ECOs (Engineering Change Orders) and LCOs (Layout Change Orders).
Constantly deliver high-quality layouts according to schedule and design requirements (matching, shielding, etc.).
Debug and resolve physical verification errors (DRC, LVS, DFM, ESD, EMIR, Antenna, Latchup, etc.) independently.
Conduct design feasibility studies to evaluate design goals for area, resources, schedule, and performance.
Collaborate with stakeholders if there are any issues and proactively provide resolution.
Contribute to methodology improvements.

QUALIFICATIONS

At least 5 years of solid experience in IC layout design.
Proficient in EDA tools like Cadence and Synopsys.
Proven experience in Latchup and ESD layout techniques and methodologies
In-depth experience in physical verification flows (DRC, LVS, DFM, ESD, EMIR, Antenna, Latchup, etc.).
Knowledgeable in SKILL scripting.
In-depth analog skill is a plus.
Experience and background in FinFET layout design are pluses.
Highly motivated, proactive, hardworking, and keen attention to detail.
Ability to communicate effectively with multi-functional teams
Good team player.
Willing to work in Alabang, Muntinlupa City.
Willing to travel to the U.K./U.S./Europe