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EXPERIENCED DESIGN VERIFICATION
(DV) ENGINEER
We are seeking an experienced Design Verification (DV) Engineer to join our team. The ideal candidate will be responsible for leading and executing verification projects, ensuring the functionality and reliability of digital designs. They will have a proven track record in RTL design, familiarity with UVM methodologies, and the ability to collaborate effectively with cross-functional teams. Strong problem-solving skills and excellent communication abilities are essential.
QUALIFICATIONS
• Proven ability to architect and lead IP/SoC-level verification projects, digital logic design and implementation in advanced technology nodes.
• Proven track record in working with teams involved in a wide variety of system disciplines (SoC Designers, micro-architects, firmware, etc.) to formulate, implement and execute verification plans and strategies.
• Working experience in UVM, embedded C-based firmware co-simulation, and formal property verification.
• Experience in any of the following Languages: C, C++/System C, PERL, Python, Java, Verilog/VHDL, SystemVerilog.
• Familiarity with or Experience in two or more of the following:
- ASIC/SOC Design Flows including Synthesis, DFT, STA, UPF, and ECO flows;
- Low Power design techniques;
- NVMe, SATA, PCIe, DDR, or ARM standards;
- Big Box Emulation platforms;
- Formal Verification methods.
• Robust debugging and problem-solving skills supported by relevant experience.
• Excellent written and verbal communication skills.
• Having an active nonimmigrant US visa or Canada visa/eTA is a plus.
• Those with ~10+ years DV experience plus Technical and/or People Leadership skills may qualify as Senior DV Engineer.